The present invention is in the field of integrated circuits (ICs) and pertains in particular to a new memory cell suitable for use in programmable logic devices for configuration control.
Arrangements of transistors in ICs to act as storage locations for binary bits (memory cells) are very well known in the art, and several different arrangements are used for different purposes. It is well known, as well, that memory cells have been integrated in many different ways in many kinds of IC devices. One such device is known as a programmable logic array (PLA), wherein memory cells are used to store bit strings that configure the PLA, that is, that program the PLA to one of the many purposes to which it may be applied. By storing different words in different patterns of memory cells in a PLA, the PLA can be configured to operate in a variety of different ways. Many reference books are available with information on both memory cells and PLAs.
In a PLA the characteristics of the memory cells are quite important. For example, the characteristics of the memory cell structure influence the power requirement and time for power up. Further, in operation of a PLA the state of the memory cells is frequently read for a variety of reasons. The characteristics of the cell structure determine the stability of cells during read operations. If a cell is relatively unstable, it may be flipped to the alternate state during a read operation.
In addition to the above, it is often desirable to alter the pattern of memory words stored in the memory cells in the PLA, to change the configuration of the PLA. In this process it is also desirable to reset the memory structure, that is, to drive all memory cells to a xe2x80x9c1xe2x80x9d condition, or all to a xe2x80x9c0xe2x80x9d condition, and then to write new data to the cells. The energy required to flip a single cell is vastly multiplied at reset because there are a very large number of memory cells in a state-of-the-art PLA. Flipping all cells results in a large current requirement. Without special design considerations in the memory system, current designs have a requirement that relatively small groups of cells may be written simultaneously.
What is clearly needed is a new and robust memory cell design that is stable for read operations, and at the same time requires a relatively low energy to flip the cell during a write operation. Just such a cell structure and operation is described in enabling detail below.
In a preferred embodiment of the present invention a Programmable Logic Array (PLA) having an operating voltage of Vcc, and a configuration memory is provided, comprising a plurality of memory cells each having first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage-controlled Vmm line, a passgate transistor for each of the plurality of cells, the passgate transistor connected source-to-drain from a BIT line to the first inverter output, the passgate having a strength sufficiently low that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch, and circuitry for reducing the voltage of Vmm during write operations so a signal on the BIT line may flip the latch through the passgate. The weak passgates reduce effect on the Q and QB nodes of the memory cells during read operations sufficiently that the PLA can be operated during configuration memory read operations.
In another aspect a Programmable Logic Array (PLA) having a nominal operating voltage is provided, comprising a configuration memory writable in specific control patterns, and an array of configurable programmable logic devices selectable by the configuration memory to perform specific tasks according to individual ones of the specific control patterns. The PLA is characterized in that the configuration memory comprises cells each having Q and QB nodes and an intentionally weak passgate, and a controlled-voltage node connected for powering the Q and QB nodes, such that the voltage on the nodes may be lowered substantially below the nominal operating voltage during writes to facilitate flipping latches by the weak passgate, and also characterized in that, with the voltage on the nodes raised to substantially the nominal operating voltage during read operations, the Q and QB nodes are unaffected by the weak passgate, allowing the PLA to operate during read operations.
In still another aspect of the invention, for a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation is provided, comprising the step of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak pass gate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches.
In yet another aspect of the invention a Programmable Logic Array (PLA) is provided comprising a configuration memory having a plurality of memory cells each having first and second inverters connected input to output to make a latch defining a Q node and a QB node, and a passgate transistor for individual ones of the plurality of cells, the passgate transistor connected source-to-drain from a BIT line to the first inverter output, the passgate having a strength sufficiently low during READ operations that the execution of the READ operation has no substantial effect on the PLA function controlled by the Q and QB nodes of the memory cells.
With the advent of the inventions taught herein in enabling detail below, for the first time a PLA is provided to the art in which PLA functions and operations may reliably continue during the same time that memory reads are made on the configuration memory, to accomplish such as memory content verification.